Quoting from CNet News:
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One performance problem comes because operating systems are accustomed to handling a part of the chip called the translation lookaside buffer, or TLB, which converts an operating system’s relative memory addresses into the actual addresses used by the hardware. But with a hypervisor actually in charge of memory, virtualization adds a second level of translation to the task.To deal with the situation, hypervisors use software called shadow paging. “It’s complex to implement and can be fairly slow,” Sander said. Barcelona technologies, including “nested page tables” and the caching of memory addresses, speeds up the memory issue.
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In addition, Barcelona has new instructions that shorten the chip’s “world switch time,” when it switches from guest operating system mode to hypervisor mode and back. Such a switch typically takes about 1,000 to 2,000 processor cycles, but the new instructions shorten that by about 25 percent, Sander said.
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In addition, he said Barcelona has dual memory controllers to read and write data from memory. That’s the same number as current Opterons, but with Barcelona, the memory controllers will be able to operate independently, he said…
Read the whole article at source.
Update: ExtremeTech has published an extended description of the new processor architecture. Worth to check it.